August 2023 · 6 min read

Why RISC-V for an OS Project

When we started FRISC OS, we chose RISC-V over x86 and ARM. Here's why.

x86: a museum of backward compatibility

x86 has real mode, protected mode, long mode, A20 gate hacks, segmentation, and decades of legacy. Writing a bootloader means dealing with BIOS, UEFI, or both. The instruction set is enormous and irregular. It's possible — Linux does it — but it's not where you want to learn OS development.

ARM: great hardware, proprietary ISA

ARM chips are everywhere, but the ISA is licensed. Documentation requires NDAs for some extensions. The boot process varies wildly between SoCs. Every board is different.

RISC-V: the clean slate

• Open ISA — no licenses, no NDAs, full spec is free
• Simple — base integer ISA (RV64I) is ~50 instructions
• QEMU support — excellent virt machine for development
• Clean privilege model — M-mode, S-mode, U-mode, clearly separated
• Growing ecosystem — SiFive boards, StarFive, Milk-V

The tradeoffs

RISC-V hardware is still immature. Real boards are expensive and slow compared to ARM. The extension ecosystem (V for vectors, H for hypervisor) is still stabilizing. But for an educational OS project running on QEMU, these don't matter.

Would we choose differently today?

No. RISC-V was the right call. The simplicity of the ISA let us focus on OS concepts instead of ISA quirks. And with QEMU, we can test on any developer machine without buying hardware.

The ISA advantage

RISC-V's base integer ISA (RV64I) has only 47 instructions. Compare that to x86-64's 1,500+ instructions. For an educational OS, this matters enormously:

• Readable disassembly — when debugging, you can read RISC-V assembly like pseudocode. x86 disassembly requires constant reference to Intel manuals.
• Predictable encoding — all RISC-V instructions are 32 bits wide (in the base ISA). No variable-length encoding means simpler disassemblers and binary analysis tools.
• Clean privilege model — three privilege levels (Machine, Supervisor, User) with clear, documented CSRs (Control and Status Registers). No legacy compatibility warts.

QEMU's virt machine

QEMU provides a standardized virtual machine for RISC-V called virt. It includes:

# Standard QEMU virt memory map (we rely on this)
# 0x0000_0000 - Debug/Test
# 0x0010_0000 - CLINT (Core Local Interruptor) — timers, IPIs
# 0x0C00_0000 - PLIC (Platform-Level Interrupt Controller)
# 0x1000_0000 - UART (NS16550A compatible)
# 0x1000_1000 - VirtIO devices (block, net, GPU, input)
# 0x8000_0000 - RAM start (configurable size)

# Launch FRISC:
qemu-system-riscv64     -machine virt     -bios none     -kernel frisc.elf     -m 128M     -nographic     -serial mon:stdio

Every address is documented. Every device has an open specification. Compare this to real x86 hardware where you need vendor NDAs to access documentation for many peripherals.

Extension modularity

RISC-V's modular extension system means we can teach concepts incrementally:

• RV64I — base integer instructions. Enough for a basic kernel with process scheduling.
• M extension — hardware multiply/divide. We started without this, implementing multiplication in software, then showed the performance gain of enabling it.
• A extension — atomic operations (LR/SC, AMO). Required for SMP. We built single-core first, then added atomics for the multi-core post.
• F/D extensions — floating point. Not used in FRISC (no need for float in a kernel), but available if students want to add it.
• C extension — compressed 16-bit instructions. Reduces code size by ~25%. Good for embedded targets.

Real hardware is coming

When we started FRISC, RISC-V was purely academic. That's changing fast:

• SiFive HiFive Unmatched — the first desktop-class RISC-V board. FRISC boots on it with minimal changes (real UART instead of VirtIO).
• StarFive VisionFive 2 — a $65 RISC-V SBC comparable to Raspberry Pi. Runs FRISC with the VirtIO drivers replaced by real device drivers.
• Milk-V Mars — another affordable board that can run FRISC.
• RISC-V laptops — the DC-ROMA and Framework RISC-V mainboard are making RISC-V laptops a reality. FRISC on bare-metal laptop hardware is a goal for 2026.

Everything we teach in FRISC on QEMU transfers directly to real silicon. The ISA is the same. The privilege model is the same. Only the device drivers change.